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The HEDC2
FEC Unit, from TEPartners, is a Forward Error Correction unit
containing the Data Encoder in Part A and the Data Decoder/Error
Corrector in part B. Part A contains a single FPGA, two RS-232C
driver and receiver ICs, and a voltage regulator IC. Part B contains
a single FPGA, a 128K Byte SRAM IC, two RS-232C driver and receiver
ICs, and a voltage regulator IC. The HEDC2 combines the latest
in FPGA technology with a unique combination of multiple implementations
of a single H.Code algorithm to produce an FEC Unit Pair with
continuously operating multi-level error detection and correction
processing.
| HEDC2
FEC Unit Pair key attributes: |
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Operates in either the Simplex mode.
- Uses
asynchronous, serial RS-232C I/O with hardware flow control.
- All
RS-232C data transfers use a bit rate of 115,200 bps with
an 8-1-N format.
- Operates
with communication channel flow control at an average
data rate of up to 88.4 Kbps.
- Includes
continuous automatic synchronization.
- Handles
long packets with greater than 512 data bytes.
- Uses
a single 3.3volt power supply.
- Provides
multiple data output lines for:
1. Minimum latency with no error correction processing,
2. Small latency with one round of error correction processing,
3. Larger latency with two rounds of error correction
processing, and
4. Connection to a second Part B Unit for further rounds
of error correction processing.
- EDAC
overhead of ~6%.
- Synchronization
overhead of <0.1%.
- Single
round of error correction processing can correct any error
pattern in a burst of up to 102 bits.
- Two
rounds of error correction processing can correct multiple
bit and burst error patterns in a burst of up to a single
burst error pattern as long as 7,100 bits.
- Will
reduce channel bit errors from a probability of up to
10-4 to virtually zero errors in the output data stream.
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| HEDC2
FEC Unit Pair benefits: |
-
Highest number of valid data bits per transmission.
- Reduced
need for retransmissions.
- No
redundancy transmissions.
- Lower
implementation cost.
- Smaller
volume/area allocation.
- Faster
product design cycle.
- Unique
EDAC algorithms.
- High-speed
operations.
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HEDC1™,
an H.Code™ Technology FEC Unit
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